1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices and particularly to a semiconductor integrated circuit device, used in a manner in which output terminals of at least two such devices are connected together. The invention has particular applicability to semiconductor memories such as dynamic random access memories.
2. Description of the Prior Art
In recent years, semiconductor memories have been frequently utilized for image processing. Particularly, in the technical fields of image processing, a plurality of semiconductor memories are used for image processing and data stored in the memories are required to be output at high speed.
FIG. 1 is a conceptional diagram showing a conventional image processing system including a plurality of semiconductor memories. Referring to FIG. 1, this image processing system comprises a plurality of memory devices 20a to 20c for image processing, a digital-to-analogue (D/A) converting portion 42 for converting data signals from the memory devices 20a to 20c to analogue signals, a display portion 43 for displaying an image based on the analogue signals, and a control portion 41. The memory devices 20a to 20c are connected to receive output control signals OEa to OEc, respectively, from the control portion 41 and respective outputs thereof are connected together to an input of the D/A converting portion 42.
In operation, the memory devices 20a to 20c successively output successively signals stored therein in response to the signals OEa to OEc, respectively, supplied from the control portion 41. The output signals are converted to analogue signals by the D/A converting portion 42 and supplied to the display portion 43.
FIG. 2 is a block diagram showing an example of a conventional dynamic random access memory (referred to hereinafter as DRAM). This DRAM is applicable to a memory device shown in FIG. 1.
The DRAM such as shown in FIG. 2 is disclosed in "A Reliable 1-M Bit DRAM with a Multi-Bit-Test Mode" by M. Kumanoya et al., 1985 (IEEE Journal Solid-State Circuits, vol. SC-20, pp. 909-913) and also in "A Fast 256K.times.4 CMOS DRAM with a Distributed Sense and Unique Restore Circuits" by Ho Miyamoto et al., 1987 (IEEE Journal Solid-State Circuits, vol. SC-22, pp. 861-867).
Referring to FIG. 2, this DRAM comprises: a memory cell array 25 for storing data signals, a row and column address buffer 21 for receiving externally applied address signals A0 to A9 for selecting a memory cell, a row decoder 22 and a column decoder 23 for designating a memory cell by decoding the address signals A0 to A9, a sense refresh amplifier 24 for amplifying the signal stored in the designated memory cell, a data-in buffer 26 and a data-out buffer 27 for input and output of data, and a clock generator 10 for generating clock signals .PHI.1 and .PHI.2. The clock generator 10 is connected to receive a row address strobe signal RAS and a column address strobe signal CAS, applied externally. A preamplifier 29 is provided between the sense refresh amplifier 24 and the data-out buffer 27. The data-out buffer 27 is connected to receive an output enable signal OEa applied externally through a terminal 10a receiving the output enable signal.
In operation, the data signal stored in the memory cell designated by the address signals is read out by the sense refresh amplifier 24 and then supplied to the data-out buffer 27 through the preamplifier 29. The data-out buffer 27 outputs the data signal in response to the signal OEa and the clock signal from the clock generator 10.
FIG. 3 is a circuit diagram showing data-out buffers in the respective DRAMs as shown in FIG. 2. A circuit similar to the data-out buffer circuit shown in FIG. 3 is indicated, for example in an analysis report of 1986 on 1M DRAM published by MOSAID-INC. Referring to FIG. 3, DRAMs 20a to 20c have output terminals connected together as shown in FIG. 1. The DRAMs 20a to 20c comprise data-out buffers 27a to 27c, respectively, which are identical tri-state buffers. For example, the data-out buffer 27a comprises NOR gates 3a and 4a each having two inputs, N channel enhancement type MOS transistors 1a and 2a connected in series between a power supply Vcc (+5 volts) and the ground Vss (0 volt), and an inverter 5a. The NOR gates 3a and 4a are connected to receive the output enable signal OEa through respective inputs on one side thereof. The NOR gate 4a is connected to receive, at the other input thereof, a signal Sai from the preamplifier 29, while the NOR gate 3a is connected to receive, at the other input thereof, the signal Sai from the preamplifier 29 through the inverter 5a. Outputs of the NOR gates 3a and 4a are connected to respective gates of the transistors 1a and 2a. The other data-out buffers 27b to 27c also have the same circuit configuration.
In operation, for example, if the signal OEa of low level is applied to the data-out buffer 27a of the DRAM 20a, the NOR gates 3a and 4a invert the signals applied to the respective other inputs thereof and output the inverted signals. More specifically, the NOR gate 3a supplies the data signal Sai from the preamplifier 29 to the gate of the transistor 1a through the inverter 5a because the above-mentioned other input of the NOR gate 3a is connected to the inverter 5a, while the NOR gate 4a supplies the inverted data signal Sai to the gate of the transistor 2a. Consequently, when the signal Sai is at high level, the transistor 1a is turned on and the transistor 2a is turned off, whereby a signal Sao of high level is output. When the signal Sai is at low level, the transistor 1a is turned off and the transistor 2a is turned on, whereby the signal Sao of low level is output.
On the other hand, if the signal OEa of high level is applied to the data-out buffer 27a, both the NOR gates 3a and 4a output signals of low level irrespective of the level of the signal Sai. Consequently, the transistors 1a and 2a are both turned off and the output terminal 9a is brought into a high-impedance state, that is, a floating state.
FIGS. 4A and 4B are timing charts for explaining operation of the DRAMs 20a and 20b, the output terminals of which are connected together. As described previously, when the DRAMs are applied to an image processing system, the output terminals of the DRAM 20a to 20c are connected together. The DRAM 20a to 20c successively output data signals stored therein, in response to the output enable signals OEa to OEc applied thereto, respectively. However, if timing of application of the signals OEa to OEc is not suitably controlled, the following disadvantages are brought about.
FIG. 4A shows a case in which data signals Sao and Sbo from two DRAMs 20a and 20b are output simultaneously in a certain period. This phenomenon occurs when the output enable signals OEa and OEb are simultaneously at a low level. More specifically, the DRAM 20a outputs data D1 in response to the signal OEa of low level. On the other hand, the DRAM 20B outputs data D2 in response to the signal OEb. The data D1 is first provided (in a period t1) and then the data D2 is provided as a common output signal SO (in a period t3) from a node where the respective output terminals of the two DRAMs are connected together. However, as can be seen from the figure, there exists a period (t2) in which the data D1 and D2 are output simultaneously. In this period t2, an accurate common output signal So cannot be obtained. In addition, if the data D1 and D2 as provided by turn-on of the transistors 1a and 2b in FIG. 3, for example, are output in the period t2, a large penetration current flows from the power supply Vcc of the DRAM 20a to the ground Vss of the DRAM 20b through the terminals 9a and 9b. As a result, consumption of electric power is increased.
FIG. 4B shows a case in which the data signals Sao and Sbo from the two DRAMs 20a and 20b are output with a long time interval. This means that the output enable signals OEa and OEb of low level are supplied with a long time interval therebetween. Consequently, as can be seen from the figure, there exists a long period (t2')in which neither the data D1 nor the data D2 is output. In this period, the output terminals 9a and 9b of the two DRAMs 20a and 20b are both in the floating state as described above and, accordingly, the common output signal So is likely to be affected by external noise. Therefore, an accurate common output signal So cannot be obtained in this period t4.
As described above, although it is necessary to apply the output enable signals with optimally controlled timing to the DRAMs having the output terminals connected together, the timing control is difficult and an accurate common output signal So cannot be obtained.